Download e-book for kindle: Analog Circuit Design: Fractional-N Synthesizers, Design for by Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing
By Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing
This ebook includes the contribution of 18 tutorials of the twelfth Workshop on Advances in Analog Circuit layout. it truly is quantity 12 within the profitable sequence of Analog Circuit layout, supplying worthy details and ideal overviews of analog circuit layout, CAD, and RF structures. The sequence could be noticeable as a connection with these fascinated by analog and mixed-signal layout. each one ebook discusses 3 particular subject matters on new and useful layout rules within the quarter of analog circuit layout. every one subject is mentioned by way of six specialists within the box and cutting-edge info is shared and overviewed. during this twelfth variation the themes are Fractional-N Synthesizers, layout for Robustness, and Line and Bus Drivers. Analog Circuit layout is a necessary reference resource for analog layout engineers and researchers that desire to hold abreast with the most recent advancements within the box. the educational assurance additionally makes it compatible to be used in a sophisticated layout path.
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Additional info for Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers
Riley, C. Plett, and M. Copeland, “An agile ISM band frequency synthesizer with built-in GMSK data modulation,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 998-1008, July 1998. S, Willingham, M. Perrott, B. Setterberg, and A. 5GHz frequency synthesizer with settling and 2Mb/s closed loop modulation,” in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 200-201. 26             B. , May 2002, pp. 425-428. R. Ahola and K. Halonen, “A 2GHz fractional-N frequency synthesizer in CMOS,” in Proc.
Englewood Cliffs, NJ: Prentice Hall, 1987. J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Data Converters. New York: IEEE Press, 1992. C. H. Heng and B. 8GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO,” in Proc. Custom Integrated Circuits Conference, May 2002, pp. 427-430. J. P. Hein and J. W. Scott, “z-domain model for discrete-time PLL’s,” IEEE Transactions on Circuits and Systems, vol. 35, pp. 1393-1400, Nov. 1988. Noel E. S. patents 4,575,867, Mar. 1986. J.
To see the dithering effect clearly, only four bits from the MSB are used for the input data of the modulator and the wide loop bandwidth of 150 kHz loop is chosen. With the 8-MHz phase detector frequency, the minimum frequency resolution is 500 kHz, which is the 1/16 of 8 MHz. In Fig. 5 MHz with the effective division ratio of 309 + 1/16. Figure 16(a) shows the fractional spur performance without dithering. Interestingly, the spur is also generated at 250-kHz offset frequency, which is half of the minimum frequency step.
Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers by Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing